Dislocation filter for semiconductor devices

US10516076B2 · kind B2 · utility

Assignee

• Silanna UV Technologies Pte Ltd · SG

Inventors

• Liam Anderson · Parramatta, AU
• William Lee · Chippewa Falls, US
• William Schaff · Ithaca, US
• Johnny Cai Tang · Parramatta, AU

Key dates

• Filing date: Feb 1, 2018
• Grant date: Dec 24, 2019
• Expiry date: Feb 1, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10H20/8215

Abstract

A dislocation filter for a semiconductor device has a buffer layer comprising a short-period superlattice (SPSL) layer. The SPSL layer has first sub-layers of a first material that alternate with second sub-layers of a second material, the first material and the second material being group III-N binary materials that are different from each other. Each of the first sub-layers and each of the second sub-layers has a sub-layer thickness less than or equal to 12 monolayers. The buffer layer also includes a third layer of a third material, the third material being a group III-N material. The SPSL forms a sandwich structure with the third layer. The buffer layer bends dislocations away from a growth direction of the buffer layer.