Memory device
US10516097B2 · kind B2 · utility
1Cited by
0References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2015 |
| Grant date | Dec 24, 2019 |
| Priority date | — |
| Expiry date | Aug 7, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/85
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The present invention provides a memory device in which lower electrodes, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, synthetic exchange diamagnetic layers, and an upper electrode are formed on a substrate in a laminated manner. According to the present invention, the lower electrodes and the seed layer are formed of a polycrystalline conductive material, and the perpendicular magnetic anisotropy of the magnetic tunnel junction is maintained upon heat treatment at a high temperature of 400° C. or more.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.