Patent · US Active

Overlay architecture for programming FPGAs

US10516396B2 · kind B2 · utility

2Cited by

1References

18Claims

0Family size

Assignee

University of Florida Research Foundation, INC. · US

Inventors

James R. Coole · Gainesville, US
Gregory M. Stitt · San Bernardino, US

Key dates

Filing date	Apr 28, 2017
Grant date	Dec 24, 2019
Priority date	—
Expiry date	May 16, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/17728
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

An overlay architecture and an associated method that uses datapath merging to provide minimal-overhead support for multiple source netlists, and optionally provides an adjustable amount of flexibility through a secondary interconnect network is disclosed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.