Interference testing
US10516439B2 · kind B2 · utility
0Cited by
3References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2017 |
| Grant date | Dec 24, 2019 |
| Priority date | — |
| Expiry date | Aug 1, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/58
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In one example a controller comprises logic, at least partially including hardware logic, configured to implement a first iteration of an interference test on a communication interconnect comprising a victim lane and a first aggressor lane by generating a first set of pseudo-random patterns on the victim lane and the aggressor lane using a first seed and implement a second iteration of an interference test by advancing the seed on the first aggressor lane. Other examples may be described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.