Current sink with negative voltage tolerance
US10520971B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2017 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | Dec 5, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2017/307
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A current sink circuit coupled to pull down a gate control node (GCN) for an NMOS power FET that controls an actuator includes first and second NMOS transistors coupled in series between the GCN and a lower rail, where the first NMOS transistor has a gate and drain coupled together through a resistor. The current sink circuit also includes a control signal generation circuit (CSGC) and a negative voltage blocking circuit (NVBC). The CSGC is coupled to receive at least one voltage input and an ignition signal and to provide a first control signal and a second control signal. The NVBC is coupled to pass the first control signal from the control signal generation circuit to the gate of the first NMOS transistor and to block a negative voltage on the GCN from reaching the CSGC. The second control signal is coupled to the gate of the second NMOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.