Polysynchronous stochastic circuits
US10520975B2 · kind B2 · utility
1Cited by
7References
22Claims
0Family size
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Key dates
| Filing date | Mar 3, 2017 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | Oct 14, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some examples, a device includes an integrated circuit and two or more computational units configured to process respective stochastic bit streams in accordance with respective input clocks. Each of the stochastic bit streams comprises sequential sets of data bits, each of the sets of data bits representing a numerical value based on a probability that any bit in the respective set of data bits is one. The respective input clocks for each of the two or more computational units are unsynchronized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.