Storage device array integration of dual-port NVMe device with DRAM cache and hostside portion of software stack system and method
US10521137B1 · kind B1 · utility
7Cited by
4References
14Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 31, 2017 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | Nov 26, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, computer program product, and computer system for receiving, by a computing device, a write I/O to a storage device array coupled to a cache, wherein the write I/O may be received from a host. A cache miss in the cache may be determined for the write I/O. One or more free pages may be allocated at an address in the cache to store data for the write I/O. The address in the cache to store the data may be sent to a hostside portion of a software stack in the storage device array. The data may be written directly from the hostside portion to the cache at the address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.