Jump page cache read method in NAND flash memory and NAND flash memory
US10521157B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Jan 15, 2018 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | Jan 15, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND flash memory including a control unit which includes a signal receiving circuit and a flash array; the signal receiving circuit is used to receive a cache read command from an external NAND controller; the flash array includes at least one chip, each chip includes at least one plane, each plane includes a plurality of blocks, each block includes a plurality of pages; when a cache read command is received, it reads pages in a first block according to an address of the page until reaching the last page in the first block; when the last page in the first block is reached, an address of a next to-be-read page is generated according to an address of the last page in the first block to allow the cache read command to read the next to-be-read page.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.