Arithmetic processing apparatus and control method for arithmetic processing apparatus
US10521346B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2018 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | Sep 4, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arithmetic processing apparatus includes, a plurality of core memory groups, each of core memory groups including a plurality of arithmetic processing circuits, cache memory circuitry, shared by the plurality of arithmetic processing circuits, including a cache memory, a cache tag that stores a state of the cache memory, a tag directory that stores data possession information by a cache memory in another core memory group, and a memory access control circuit that receives a first memory access request from the cache memory circuitry and controls access to a memory other than a cache memory included in the cache memory circuitry, and a cache memory control circuit that receives a second memory access request from the arithmetic processing circuits and a third memory access request from the another core memory group and controls access to the cache memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.