Systems and methods for implementing an intelligence processing computing architecture

US10521395B1 · kind B1 · utility

Assignee

• Mythic, Inc. · US

Inventors

• David Fick · Austin, US
• Malav Parikh · Austin, US
• Paul Toth · Daly City, US
• Adam Caughron · Austin, US
• Vimal Reddy · Raleigh, US
• Erik Schlanger · Austin, US
• Sergio Schuler · Austin, US
• Zainab Nasreen Zaidi · Austin, US
• Alex Dang-Tran · Austin, US
• Raul A. Garibay, Jr. · Plano, US
• Bryant Sorensen · Colorado Springs, US

Key dates

• Filing date: Jul 1, 2019
• Grant date: Dec 31, 2019
• Expiry date: Jul 1, 2039

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D10/00
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Systems and methods include an integrated circuit that includes a plurality of computing tiles, wherein each of the plurality of computing tiles includes: a matrix multiply accelerator, a computing processing circuit; and a flow scoreboard module; a local data buffer, wherein the plurality of computing tiles together define an intelligence processing array; a network-on-chip system comprising: a plurality of network-on-chip routers establishing a communication network among the plurality of computing tiles, wherein each network-on-chip router is in operable communication connection with at least one of the plurality of computing tiles and a distinct network-on-chip router of the plurality of network-on-chip routers; and an off-tile buffer that is arranged in remote communication with the plurality of computing tiles, wherein the off-tile buffer stores raw input data and/or data received from an upstream process or an upstream device.