Resistive memory device for matrix-vector multiplications
US10522223B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 4, 2018 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | Jul 4, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A matrix-vector multiplication device includes a memory crossbar array with row lines, column lines, and junctions. Each junction comprises a programmable resistive element and an access element. A signal generator is configured to apply programming signals to the resistive elements to program conductance values for the matrix-vector multiplication and a readout circuit is configured to apply read voltages to the row lines and to read out current values of the column lines. Control circuitry is configured to control the signal generator and the readout circuit and to select, via the access terminals, a plurality of resistive elements in parallel according to a predefined selection scheme which applies the signals and/or the read voltages in parallel to resistive elements which do not share the same row and column line and applies the programming signals and/or the read voltages to at most one resistive element per row line and column line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.