Method of creating aligned vias in ultra-high density integrated circuits
US10522394B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2018 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | Aug 21, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1015
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming vias aligned with metal lines in an integrated circuit is provided. The method includes: forming a stacked dielectric, capped, hard mask, and first film and photoresist layers; patterning first photoresist layer to provide metal line masks; etching hard mask layer based on patterned first photoresist layer to form metal line masks; ashing first photoresist and film layers; forming second film and photoresist layers on hard mask layer; patterning second photoresist layer to form via masks across opposing sides of metal line masks; etching second film and capped layers based on patterned second photoresist layer; ashing second photoresist and film layers; etching dielectric and capped layers based on a pattern of hard mask layer to provide via and metal line regions; etching hard mask and capped layers; and performing dual damascene process operations to form vias and metal lines in via and metal line regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.