Three-dimensional transistor

US10522619B2 · kind B2 · utility

Assignees

• Semiconductor Manufacturing International (Beijing) Corporation · CN
• Semiconductor Manufacturing International (Shanghai) Corporation · CN

Inventors

• Xinyuan Lin · Tianjin, CN
• Ying Jin · Shanghai, CN

Key dates

• Filing date: Sep 18, 2017
• Grant date: Dec 31, 2019
• Expiry date: Sep 18, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6212
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The disclosed subject matter provides a method for fabricating a three-dimensional transistor. The method includes forming an active region and two isolation structures on a semiconductor substrate. The active region is formed between the two isolation structures. The method further includes forming a photoresist layer on the active region and the isolation structures, forming an opening in the photoresist layer to expose a top surface of the active region and a portion of a top surface of each isolation structure, and then forming a trench on each side of the active region by removing a portion of the corresponding isolation structure exposed in the opening through an etching process using the photoresist layer as an etch mask. After the etching process, the portion of the active region between the two trenches becomes a three-dimensional fin structure. The disclosed method simplifies fabrication process for three-dimensional transistors and reduces product cost.