Forming epitaxial structures in fin field effect transistors
US10522656B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2018 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | Feb 28, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming source/drain features in a FinFET device includes providing a fin formed over a substrate and a gate structure formed over a fin, forming a recess in the fin adjacent to the gate structure, forming a first epitaxial layer in the recess, forming a second epitaxial layer over the first epitaxial layer, and forming a third epitaxial layer over the second epitaxial layer. The second epitaxial layer may be doped with a first element, while one or both of the first and the third epitaxial layer includes a second element different from the first element. One or both of the first and the third epitaxial layer may be formed by a plasma deposition process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.