Optimized pin pattern for high speed input/output
US10522949B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2018 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | Aug 8, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10704
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Pin layouts for HSIO require a large number of pins due to isolation requirements. Differential signaling can be used in high speed transmission and reception. A single lane for operation at 6 to 8 Gbps speed typically a total of six to eight pins. At higher speeds, conventional technique to meet isolation requirements is to increase the number of ground pins per lane. With many lanes, the number of pins can become cumbersome. To address such issues, it is proposed to provide pin patterns that leverage differential cancellation to enhance signal isolation so that operation speed can increase while also reducing the number of pins so that the number of pins of a package is less cumbersome.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.