Adaptive power saving in field programmable gate array (FPGA) in optical module
US10523203B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 16, 2016 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | Aug 8, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0315
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for saving power in an field programmable gate array (FPGA) in an optical communication device is provided. The apparatus includes at least one ring oscillator having an operating frequency disposed inside the FPGA, a core voltage switching unit configured to supply a core operating voltage to the FPGA, and control logic configured to adaptively output an adjusted new core voltage to the FPGA via the core voltage switching unit. The control logic is configured to output a core voltage control signal to the core voltage switching unit based on the operating frequency of the at least one ring oscillator. The core voltage switching unit is further configured to supply the adjusted new core voltage to the FPGA in accordance with the core voltage control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.