Techniques for signal skew compensation
US10523224B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2019 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | May 16, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0995
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a signal network and a phase detector circuit. The signal network includes an adjustable delay circuit. The adjustable delay circuit is coupled at an intersection in the signal network between branches of the signal network. The signal network generates a first signal at a first leaf node of the signal network in response to a second signal. The signal network generates a third signal at a second leaf node of the signal network in response to the second signal. The phase detector circuit compares phases of the first and third signals to generate a phase detection signal. The adjustable delay circuit adjusts a delay provided to the first signal relative to the second signal to reduce a skew between the first and third signals based on the phase detection signal indicating that the first and third signals have the skew.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.