System and methods for mixed-signal computing
US10523230B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2019 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | Jul 2, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45551
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.