Clock and data recovery circuit
US10523414B2 · kind B2 · utility
1Cited by
2References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2019 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | Apr 17, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.