Interface circuitry
US10523472B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2018 |
| Grant date | Dec 31, 2019 |
| Priority date | — |
| Expiry date | Oct 2, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0328
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Aspects of the disclosure provide an apparatus that includes interface circuitry with a serializer/deserializer (SERDES) circuit. The interface circuitry includes a receiving circuit that receives a signal that carries a sequence of digital values. The receiving circuit includes sampler circuit and a feedback equalization circuit. The sampler circuit includes an amplifying portion and a latch portion coupled at an intermediate node. The amplifying portion varies, with an amplifying gain, an intermediate signal at the intermediate node in response to an input signal to the sampler circuit, and the latch portion generates a digital output based on the intermediate signal at the intermediate node. The feedback equalization circuit is coupled to the intermediate node to vary the intermediate signal at the intermediate node based on a previous digital output from the latch portion of the sampler circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.