Hardware debug host
US10527673B2 · kind B2 · utility
3Cited by
13References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2017 |
| Grant date | Jan 7, 2020 |
| Priority date | — |
| Expiry date | Oct 23, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3656
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A hardware debug system includes a target chip comprising one or more target chip registers and one or more target chip ports, wherein at least one of the one or more target chip ports is used as a target chip debug port, and a debug host with one or more debug host ports, wherein at least one of the one or more debug host ports is connected to the target chip debug port via a hardware debug bus, wherein the debug host is configured to load at least one target chip setting into the one or more target chip registers that enables the target chip to boot via the hardware debug port using the hardware debug bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.