Patent · US Active

Phase compensated PLL

US10528009B2 · kind B2 · utility

0Cited by
5References
22Claims
0Family size

Assignee

Inventor

Key dates

Filing dateMay 24, 2018
Grant dateJan 7, 2020
Priority date—
Expiry dateMay 24, 2038

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03L2207/50
  • WIPO fieldBasic communication processes
  • WIPO sectorElectrical engineering

Abstract

A phase locked loop comprising a time to digital converter and a fractional-n feedback loop, the PLL being configurable by a phase compensator module to reduce the dynamic range of the TDC required to maintain PLL performance.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.