Instruction processing alignment system
US10528077B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2017 |
| Grant date | Jan 7, 2020 |
| Priority date | — |
| Expiry date | Feb 15, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1695
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for synchronizing processor units. An external synchronizer is communicated with to determine whether an undesired amount of skew is present between a first processor unit and a second processor unit in communication with a synchronization system. The first processor unit is selectively directed to perform an action without generating a needed result such that the undesired amount of skew between the first processor unit and the second processor unit is reduced when the undesired amount of skew is present in the first processor unit. The first processor unit and the second processor unit are associated with each other for a high integrity mode in which integrity checks are performed on corresponding messages generated by the first processor unit and the second processor unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.