Criticality-based error detection

US10528413B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Jun Tan · Kepong, MY
• Kiun Kiet Jong · Merang, MY

Key dates

• Filing date: Apr 3, 2017
• Grant date: Jan 7, 2020
• Expiry date: Oct 22, 2037

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2119/12
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A prioritized error detection schedule may be generated using computer-aided-design (CAD) tools that receive specifications of critical regions within an array of configuration random access memory (CRAM) cells on an integrated circuit. Each of the specified critical regions may be provided a respective criticality weight. The proportion of indices in a prioritized error detection schedule that prescribe error detection for a given critical region may be based on the criticality weight of the given critical region. A prioritized error detection schedule may prescribe more frequent error correction for critical regions with higher criticality weights relative to critical regions with lower criticality weights. Addressing circuitry on the integrated circuit may be used to read out data from critical regions of CRAM in the order prescribed by the prioritized error detection schedule and check the read out CRAM data for errors.