Validation of multiprocessor hardware component
US10528443B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jan 30, 2015 |
| Grant date | Jan 7, 2020 |
| Priority date | — |
| Expiry date | Dec 31, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3055
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, apparatus and computer program product to be employed by a hardware component under validation, wherein the hardware component having a plurality of processing units each belonging to one of at least two types, such that one of the at least two types of processing units is less error-prone than a remainder of the at least two types. The method comprising: designating one of the processing units of the hardware component under validation that belongs to the less error-prone type as a manager processing unit; initiating execution of a tester program code for testing processing units, by processing units of the hardware component other than the manager processing unit; and, monitoring by the manager processing unit the status of the processing units during execution of the tester program code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.