Semiconductor device
US10529866B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2012 |
| Grant date | Jan 7, 2020 |
| Priority date | — |
| Expiry date | May 30, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/116
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An SOI or PSOI device including a device structure having a plurality of doped semiconductor regions. One or more of the doped semiconductor regions is in electrical communication with one or more electrical terminals. The device further includes an insulator layer located between a bottom surface of the device structure and a handle wafer. The device has an insulator trench structure located between a side surface of the device structure and a lateral semiconductor region located laterally with respect to the device structure. The insulator layer and the insulator trench structure are configured to insulate the device structure from the handle wafer and the lateral semiconductor region, and the insulator trench structure includes a plurality of insulator trenches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.