Memory structure for use in resistive random access memory devices and method for use in manufacturing a data storage device
US10529921B2 · kind B2 · utility
1Cited by
6References
33Claims
0Family size
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Key dates
| Filing date | Jun 3, 2016 |
| Grant date | Jan 7, 2020 |
| Priority date | — |
| Expiry date | Jun 3, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/71
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory structure for use in a memory device comprising at least one first layer and at least one second layer: the at least one first layer comprises a plurality of a first element, and the at least one second layer comprises a plurality of a second element; and, wherein the memory structure has an electrical resistive state that can be changed in response to an electromotive force being applied thereto.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.