Memory device having hybrid insulating layer and method for preparing same
US10529936B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2016 |
| Grant date | Jan 7, 2020 |
| Priority date | — |
| Expiry date | Aug 23, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K10/40
Abstract
The present disclosure relates to a memory device having a hybrid insulating layer and a method for preparing the same. In detail, a memory device including a gate electrode on a substrate, a source electrode, and a drain electrode has a hybrid memory insulating layer between the gate electrode and the source and drain electrodes that is polarizable and includes a mixed material of vinyltriethoxysilane and organic matter to lead to hysteresis. According to the present disclosure, a memory insulating layer is formed as a hybrid insulating layer including a mixture of polyvinylphenol as the organic matter and vinyltriethoxysilane to complement the properties of an organic memory whereby increasing memory performance, and it stably operates at both low and high temperatures whereby having a wide usage range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.