Patent · US Active

Predictive dead time generating circuit

US10530258B1 · kind B1 · utility

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9Claims

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Assignee

University of Electronic Science and Technology of China · CN

Inventors

Zekun Zhou · Chengdu, CN
Yunkun Wang · Chengdu, CN
Yandong Yuan · Chengdu, CN
Shilei Li · Beijing, CN
Zhuo Wang · Suzhou, CN
Bo Zhang · Shanghai, CN

Key dates

Filing date	Apr 24, 2019
Grant date	Jan 7, 2020
Priority date	—
Expiry date	Apr 24, 2039

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02B70/10
WIPO fieldElectrical machinery, apparatus, energy
WIPO sectorElectrical engineering

Abstract

A predictive dead time generating circuit includes a dead time detecting module configured to detect a dead time between the switching off of the upper power transistor and the switching on of the lower power transistor, and a dead time between the switching off of the lower power transistor and the switching on of the upper power transistor, and to generate a first detecting signal and a second detecting signal according to the condition of whether the detected dead time reaches an optimal value. The logic control module changes the output of the delay module according to the judgment result of the dead time detecting module, so as to change the dead time between the driving signal of the upper power transistor and the driving signal of the lower power transistor.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.