Clock distribution
US10530342B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2019 |
| Grant date | Jan 7, 2020 |
| Priority date | — |
| Expiry date | Jan 9, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Clock distribution circuitry configured for duty cycle control, the circuitry comprising: a plurality of buffers connected in series along a clock path, each of the buffers having an input terminal and an output terminal, the input terminal being connected to the clock path via a corresponding AC coupling capacitor, and the clock, path configured to receive an input clock signal at its input node and output an output clock signal at its output node, the output clock signal having an output duty cycle; and control circuitry connected to apply a DC bias signal to the input terminal of each of the plurality of buffers, wherein the control circuitry is configured to: obtain a measurement signal indicative of the output duty cycle; and control the DC bias signals, based on a difference between the measurement signal and a reference signal, so as to control the output duty cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.