Patent · US Active

Short link efficient interconnect circuitry

US10530614B2 · kind B2 · utility

4Cited by

0References

22Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Hsinho Wu · Santa Clara, US
Masashi Shimanouchi · San Jose, US
Peng Li · Beijing, CN

Key dates

Filing date	Dec 21, 2018
Grant date	Jan 7, 2020
Priority date	—
Expiry date	Dec 21, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH04L2025/03802
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

Systems and methods for electronic devices including two or more semiconductor devices coupled via an interconnect. The interconnect includes multiple lanes each having a link between the first and second semiconductor devices. One or more lanes of the multiple lanes each include clock and data recovery circuitry to perform full clock and data recovery. One or more other lanes of the multiple lanes each do not include clock and data recovery circuitry and instead includes a phase adjustment and clock multiplier circuit that is slave to clock and data recovery circuitry of the one or more lanes.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.