Array substrate and display panel
US10534234B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2018 |
| Grant date | Jan 14, 2020 |
| Priority date | — |
| Expiry date | Jun 4, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2300/0452
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present disclosure provides an array substrate and a display panel containing the array substrate. The array substrate includes a plurality of pixel regions, and pixel electrodes and thin film transistors one-to-one corresponding thereto. Each pixel electrode includes a pixel sub-electrode and an electrode connecting structure disposed in a corresponding pixel region, and a drain electrode of each thin film transistor is electrically connected to a corresponding pixel sub-electrode. The plurality of pixel regions includes at least one first-color pixel region and at least one second-color pixel region alternately arranged along a first direction and at least one third-color pixel region and at least one highlight pixel region alternately arranged along a first direction. A drain electrode is electrically connected to a pixel sub-electrode disposed in one of the at least one third-color pixel region is disposed in a highlight pixel region adjacent to the third-color pixel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.