Information processing apparatus, PLD management program and PLD management method
US10534621B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2018 |
| Grant date | Jan 14, 2020 |
| Priority date | — |
| Expiry date | Aug 11, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/343
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information processing apparatus has a processor and a programmable logic circuit device (PLD) that includes a reconfiguration region to configure a logic circuit requested by a configuration request from the processor. The processor compares a first execution time of a plurality of the logic circuits for a case when a degree of parallelism adjustment is performed by decreasing a degree of parallelism of a first logic circuit and increasing a degree of parallelism of a second logic circuit and a second execution time of the plurality of logic circuits for a case when the degree of parallelism adjustment is not performed, and requests the degree of parallelism adjustment to the PLD when the first execution time is shorter than the second execution time, and does not request the degree of parallelism adjustment to the PLD when the first execution time is not shorter than the second execution time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.