Array substrate and display apparatus
US10535318B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 11, 2018 |
| Grant date | Jan 14, 2020 |
| Priority date | — |
| Expiry date | Apr 11, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0252
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present disclosure is related to an array substrate. The array substrate may include a plurality of gate lines, a plurality of data lines intersecting the gate lines, and a first gate driving circuit comprising a plurality of shift register circuits in a non-active area. The gate lines and the data lines may define a plurality of sub-pixels in an active area and a plurality of dummy sub-pixels in the non-active area adjacent to the active area. The first gate driving circuit may be farther away from the active area than the plurality of the dummy sub-pixels. At least one of the dummy sub-pixels may include an auxiliary capacitor. A shift register circuit in the first gate driving circuit may be coupled to the auxiliary capacitor. The auxiliary capacitor may form at least a part of a bootstrap capacitor in the shift register circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.