Semiconductor memory devices
US10535659B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2018 |
| Grant date | Jan 14, 2020 |
| Priority date | — |
| Expiry date | Jul 17, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
Abstract
Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.