Charge-saving power-gate apparatus and method
US10536139B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2018 |
| Grant date | Jan 14, 2020 |
| Priority date | — |
| Expiry date | Apr 20, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0063
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power-gate circuit includes a power-gate transistor operable to switch to decouple a first supply voltage from a second supply voltage during an idle mode, and to couple the first supply voltage to the second supply voltage during a full operational mode. Part of the charge stored at a gate terminal of the power-gate transistor, would have been otherwise flushed to ground while turning on the power-gate transistor, is routed to the rail of the second supply voltage of the logic block. Part of the charge on the rail of the second supply voltage is used to charge the gate terminal of the power-gate transistor to deactivate the power-gate transistor if the logic block goes to the idle mode. Energy is saved both ways because of the charge recycling and the ability to use the power-gate circuit even in cases where the duration of the idle mode may be short.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.