Serializer/deserializer physical layer circuit
US10536166B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2019 |
| Grant date | Jan 14, 2020 |
| Priority date | — |
| Expiry date | Jun 11, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03J2200/11
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a Serializer/Deserializer physical layer circuit (SerDes PHY) for receiving and transmitting data in a half-duplex manner, the SerDes PHY including: a clock multiplication unit including a phase frequency detector (PFD), a charge pump (CP), a low pass filter, a voltage-controlled oscillator (VCO) and a loop divider; a sampling circuit sampling a received signal according to clocks from the VCO in a receive mode; a phase detector (PD) operating according to outputs of the sampling circuit; a multiplexer connecting the PD with the CP and disconnecting the PFD from the CP in the receive mode, and connecting the PFD with the CP and disconnecting the PD from the CP in a transmission mode; a parallel-to-serial converter converting parallel data into serial data according a clock from the VCO in the transmission mode; and a transmission driver outputting a transmission signal according to the serial data in the transmission mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.