Image sensor with tolerance optimizing interconnects
US10537234B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 5, 2018 |
| Grant date | Jan 21, 2020 |
| Priority date | — |
| Expiry date | Mar 5, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F77/124
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed. Embodiments of the above may include systems, methods and processes for staggering ADC or column circuit bumps in a column or sub-column hybrid image sensor using vertical interconnects are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.