Analog circuit fault diagnosis method using single testable node

US10539613B2 · kind B2 · utility

Assignee

• Hefei University of Technology · CN

Inventors

• Yigang He · Daguantang, CN
• Lifen Yuan · Meekrap-oord, CN
• Lei Wu · Pleasanton, US
• Yesheng Sun · Meekrap-oord, CN
• Chaolong Zhang · Hangzhou City, CN
• Ying Long · Beijing, CN
• Zhen Cheng · Hunan, CN
• Zhijie Yuan · Meekrap-oord, CN
• Deqin Zhao · Meekrap-oord, CN

Key dates

• Filing date: Nov 25, 2015
• Grant date: Jan 21, 2020
• Expiry date: Apr 27, 2036

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/3161
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

An analog circuit fault diagnosis method using a single testable node comprises the following steps: (1) obtaining prior sample data vectors under each fault mode; (2) computing a statistical average of the prior sample data vectors under each of the fault modes; (3) decomposing a signal by an orthogonal Haar wavelet filter set; (4) extracting the feature factor of the prior sample fault modes; (5) extracting a fault-mode-to-be-tested feature factor; (6) computing a correlation coefficient matrix and correlation metric parameters between the feature factor of the prior sample fault modes and the feature factor of the fault-mode-to-be-tested; and (7) determining a fault mode according to a maximal correlation principle by comparing the correlation metric parameters. The method can convert a single signal into a plurality of signals without losing original measurement information, and extract an independent fault mode feature factor reflecting variations of a circuit structure in different fault modes, can be used to study an associated mode determination rule and successfully complete classification of circuit fault modes.