Ultra-low-power design memory power reduction scheme
US10539997B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 2016 |
| Grant date | Jan 21, 2020 |
| Priority date | — |
| Expiry date | Feb 14, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosure generally relates to a memory power reduction scheme that can flexibly transition memory blocks among different power states to reduce power consumption (especially with respect to leakage power) in a manner that balances tradeoffs between reduced power consumption and performance impacts. For example, according to various aspects, individual memory blocks may be associated with an access-dependent age, whereby memory blocks that are not accessed may be periodically aged. As such, in response to the age associated with a memory block crossing an appropriate threshold, the memory block may be transitioned to a power state that generally consumes less leakage power and has a larger performance penalty. Furthermore, one or more performance-related criteria may be defined with certain memory blocks to prevent and/or automatically trigger a transition to another power state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.