JTAG lockout with dual function communication channels
US10540213B2 · kind B2 · utility
0Cited by
13References
17Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 7, 2018 |
| Grant date | Jan 21, 2020 |
| Priority date | — |
| Expiry date | Mar 31, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318588
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A Joint Test Action Group (JTAG) communication lockout processor is disclosed. The processor is configured to generate a unlock sequence based on an operational mode change of an operably connected programmable device, and save the unlock sequence to one or more memory registers. The processor can also receive an execution of the unlock sequence via a dual function JTAG communication bus, determine, via an unlock logic, whether the execution of the unlock sequence is valid, and responsive to determining that the execution of the unlock sequence is valid, allow or disallow the JTAG communication with an embedded processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.