Method and apparatus for supporting the use of interleaved memory regions
US10540277B2 · kind B2 · utility
1Cited by
1References
40Claims
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Key dates
| Filing date | Oct 15, 2014 |
| Grant date | Jan 21, 2020 |
| Priority date | — |
| Expiry date | Mar 8, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/656
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method comprising: receiving a transaction associated with an address and having a transaction destination, said address being in an interleaved region of a memory; determining one of a plurality of destinations for said transaction, different parts of said interleaved memory region being respectively accessible by said plurality of destinations; and associating routing information to said transaction, said routing information associated with the determined destination.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.