Patent · US Active

Cache-coherent multiprocessor system and a method for detecting failures in a cache-coherent multiprocessor system

US10540284B2 · kind B2 · utility

0Cited by

5References

19Claims

0Family size

Assignee

NXP USA, Inc. · US

Inventors

Dirk Wendel · Unterhaching, DE
Oliver Bibel · Grasbrunn, DE
Joachim Fader · Munich, DE
Wilhard Von Wendorff · Munich, DE

Key dates

Filing date	Jul 29, 2014
Grant date	Jan 21, 2020
Priority date	—
Expiry date	Apr 13, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/1032
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A cache-coherent multiprocessor system comprising processing units, a shared memory resource accessible by the processing units, the shared memory resource being divided into at least one shared region, at least one first region, and at least one second region, a first cache, a second cache, a coherency unit, and a monitor unit, wherein the monitor unit is adapted to generate an error signal, when the coherency unit affects the at least one first region due to a memory access from the second processing unit and/or when the coherency unit affects the at least one second region due to a memory access from the first processing unit, and a method for detecting failures in a such a cache-coherent multiprocessor system.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.