Critical path aware voltage drop analysis of an integrated circuit
US10540464B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2018 |
| Grant date | Jan 21, 2020 |
| Priority date | — |
| Expiry date | Sep 21, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present embodiments relate to critical path aware voltage drop analysis. A method can include identifying a number of cell instances with largest individual power consumption values. The method can include identifying, by performing static timing analysis, a first number of circuit timing paths of an integrated circuit design with largest timing violations. The method can include identifying, by performing the static timing analysis, a second number of circuit timing paths of the integrated circuit design. Each of the second number of circuit timing paths has a timing violation and is formed by one or more of the identified number of cell instances. The method can include generating logic state toggle vectors by propagating logic states through the first and second numbers of circuit timing paths. The method can include performing voltage drop analysis on the integrated circuit design using the generated logic state toggle vectors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.