Operating a quantum processor having a three-dimensional device topology
US10540604B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2019 |
| Grant date | Jan 21, 2020 |
| Priority date | — |
| Expiry date | May 13, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/195
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a general aspect, three-dimensional integrated multilayer architectures for qubit devices organized in quantum processors are described herein. In some aspects, a quantum processor includes devices residing in multiple physical layers. The quantum processor also includes connections that interconnect the devices in a tree structure topology. A computational state is encoded in child qubit devices in a first layer of the tree structure topology. A quantum control sequence is applied to at least one of the devices to transform the computational state. Applying the quantum control sequence includes using one or more parent qubit devices in a second layer of the tree structure topology to mediate between child qubit devices in the first layer of the tree structure topology. A readout of the transformed computational state may be performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.