Processing unit performance projection using dynamic hardware behaviors
US10540737B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2017 |
| Grant date | Jan 21, 2020 |
| Priority date | — |
| Expiry date | Apr 2, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods for estimating accelerator performance for dynamic hardware behaviors are disclosed. Computer program code to be executed on a first processing unit is received, and an execution of the computer code on the first processing unit is monitored to determine a plurality of performance characteristics. A plurality of dynamic hardware behaviors is determined by applying a clustering algorithm to the performance characteristics, and an equivalent accelerator portion of computer code to be executed on a second processing unit is generated by translating a set of instructions in a first portion of computer code corresponding to a first one of the plurality of dynamic hardware behaviors to an equivalent set of instructions to be executed on the second processing unit. An estimated measure of performance for executing the equivalent accelerator portion on the second processing unit is determined for the first one of the plurality of dynamic hardware behaviors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.