Providing efficient handling of memory array failures in processor-based systems
US10541044B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2017 |
| Grant date | Jan 21, 2020 |
| Priority date | — |
| Expiry date | Jan 24, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Providing efficient handling of memory array failures in processor-based systems is disclosed. In this regard, in one aspect, a memory controller of a processor-based device is configured to detect a defect within a memory element of a plurality of memory elements of a memory array. In response, a disable register of one or more disable registers is set to correspond to the memory element to indicate that the memory element is disabled. The memory controller receives a memory access request to a memory address corresponding to the memory element, and determines, based on one or more disable registers, whether the memory element is disabled. If so, the memory controller disallows the memory access request. Some aspects may provide that the memory controller, in response to detecting the defect, provides a failure indication to an executing process, and subsequently receives, from the executing process, a request to set the disable register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.