Printed repassivation for wafer chip scale packaging
US10541220B1 · kind B1 · utility
2Cited by
2References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2018 |
| Grant date | Jan 21, 2020 |
| Priority date | — |
| Expiry date | Aug 2, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Described examples provide integrated circuits and methods, including forming a conductive seed layer at least partially above a conductive feature of a wafer, forming a conductive structure on at least a portion of the conductive seed layer, performing a printing process that forms a polymer material on a side of the wafer proximate a side of the conductive structure, curing the deposited polymer material, and attaching a solder ball structure to a side of the conductive structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.