Integrated circuit device and method of manufacturing the same
US10541302B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2018 |
| Grant date | Jan 21, 2020 |
| Priority date | — |
| Expiry date | Jan 29, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/315
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device includes a substrate having a first region and a second region separated from each other along a direction parallel to an upper surface of the substrate. An interface device isolation layer fills an interface trench in an interface region between the first region and the second region and defines a portion of a first active area positioned in the first region and a portion of a second active area positioned in the second region. An insulation pattern extends from the first region to an upper portion of the interface device isolation layer. The insulation pattern covers the first active area and at least a portion of the interface device isolation layer. The insulation pattern defines an undercut area on an upper surface of the interface device isolation layer. A buried pattern substantially fills the undercut region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.