INP-based transistor fabrication
US10541315B2 · kind B2 · utility
0Cited by
13References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2017 |
| Grant date | Jan 21, 2020 |
| Priority date | — |
| Expiry date | Oct 12, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device are disclosed. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.